1. Field of the Invention
This invention relates generally to integrated circuit devices, and, more particularly, to a method for detecting faulty structures in integrated circuit devices.
2. Description of the Related Art
Automated semiconductor fabrication processes allow millions of integrated circuit structures to be formed on a single semiconductor die. For example, individual transistors, complex memory arrays, processor devices, and other like circuits are commonly formed on semiconductor dice. Although the automated processes are reliable, they are not perfect. The integrated circuit structures formed by automated fabrication processes may contain a variety of faults, including electrical shorts, open circuits, and the like. The faults may cause the integrated circuit structures to operate in an undesirable manner or to fail entirely.
Structures and techniques have been developed to detect faults in integrated circuit structures formed on semiconductor dice. One example of such a structure and an associated technique is illustrated in FIGS. 1A-C. FIG. 1A shows a plan view of a first exemplary integrated circuit structure 100 including a plurality of circuit elements 110 and at least two pads 120(1-2). A cross-sectional view of the integrated circuit structure 100 along the line 130 is shown in FIG. 1B. The circuit elements 110 and pads 120(1-2) are located in an insulating layer 140 and are electrically coupled by a plurality of vias 150. The insulating layer 140 also electrically isolates the circuit elements 110, the pads 120(1-2), and the vias 150 from a semiconductor substrate 160. As will be understood by those of ordinary skill in the art, the insulating layer 140 will typically comprise two or more insulating layers, with the circuit elements 100, the pads 120(1-2), and the vias 150 formed in the various insulating layers. Thus, FIG. 1B represents a simplified illustration of a structure 100.
A probe tool 170 may be electrically coupled to the pads 120(1-2). If no faults are present in the integrated circuit structure 100, the probe tool 170 will determine that the pad 120(1) is electrically coupled to the pad 120(2). However, if a fault, such as the open circuit 180 shown in FIG. 1C, is present, the probe tool 170 will determine that the pad 120(1) is not electrically coupled to the pad 120(2). Although the probe tool 170 may detect the presence of the open circuit 180, the probe tool cannot typically determine a location of the open circuit 180.
A second example of a structure and an associated technique for determining faults is illustrated. in FIGS. 2A-C. FIG. 2A shows a plan view of second exemplary integrated circuit structure 200 including a plurality of circuit elements 210 and at least two pads 220(1-2). A cross-sectional view of the integrated circuit structure 200 along the line 230 is shown in FIG. 2B. The circuit elements 210 and pads 220(1-2) are located in an insulating layer 240 and are electrically coupled by a plurality of vias 250. In the second exemplary integrated circuit structure 200, a via 255 electrically couples the pad 220(1) to a semiconductor substrate 260, which is typically coupled to an electrical ground potential 265 during testing. As in the case of the insulating layer 140 shown in FIG. 1B, the insulating layer 240 in FIG. 2B will typically comprise two or more insulating layers, with the integrated circuit structure 200 being formed in the two or more insulating layers.
In the second failure analysis technique, a scanning electron microscope (SEM) 270 irradiates the integrated circuit structure with an electron beam 275. Electrons (not shown) from the beam are deposited in the circuit elements 210, the pads 220(1-2), and the vias 250, 255. If there are no faults in the integrated circuit structure 110, the electrons flow along the integrated circuit structure 100, through the via 255 to the electrical ground potential 265. Thus, the integrated circuit structure 200 discharges to a reduced electrical charge or, in some cases, becomes electrically neutral. If a fault, such as the open circuit 280 shown in FIG. 2C, is present, electrons in a first portion of the integrated circuit structure 200 between the via 255 and the open circuit 280 flow to the ground potential 265, and this portion of the structure 200 is essentially discharged. The open circuit 280 electrically decouples the second portion of the integrated circuit structure 200, located between the open circuit 280 and the pad 220(2) and shown with shading in FIG. 2C, from the ground potential 265. Consequently, the flow of electric charge out of the second portion is reduced, or stopped, by the open circuit 280, and the second portion retains an electric charge for a longer time than the first portion.
The electric charge retained in the second portion of the integrated circuit structure 200 can be detected using known voltage contrasting techniques. Consequently, the location of the open circuit 280 may be determined using the second failure analysis technique. However, to determine if a fault exists in a structure (or a set of structures) the entire structure (or set of structures) must be scanned. This process of scanning is time consuming and costly. Moreover, the structure 200 is not readily susceptible to testing using the probe 170 of FIG. 1C because the structure 200 is grounded (through the via 255 and the substrate 260).
Conversely, the structure 100 is easily tested using the probe 170, but it cannot be analyzed using the SEM 270 and voltage contrasting techniques because no point of the structure is grounded. Hence, a technique has been developed whereby the structure 100, after testing by the probe 170 to determine the existence of a fault somewhere in the structure, may be altered to render it susceptible to analysis using the SEM 270. The technique involves boring or etching an opening through one of the pads 120(1-2), through the insulating layer 140, and to the substrate 160. This opening is then filled with a conductive material so as to electrically couple the selected pad to the substrate 160. Thereafter, the structure 100 may be analyzed in much the same way as the structure 200 of FIGS. 2A-C.
In one aspect of the instant invention, an apparatus is provided for detecting and locating a fault in an integrated circuit structure formed in one or more insulating layers deployed on a semiconductor substrate. The apparatus includes a probe tool capable of detecting a fault in the integrated circuit structure, a laser tool capable of forming an electrical connection between the integrated circuit structure and the semiconductor substrate, and a controller coupled to the probe tool and the laser tool, wherein the controller is capable of directing the laser tool to form the electrical connection between the integrated circuit structure and the semiconductor substrate in response to detecting the fault in the integrated circuit structure. The apparatus also includes a source for providing an electrical charge to the integrated circuit structure in response to detecting the fault in the integrated circuit structure and a detector for detecting an electrical charge accumulation in at least a portion of the integrated circuit structure.
In another aspect of the present invention, a method is provided for detecting and locating faults in an integrated circuit structure formed on a substrate. The method includes probing the integrated circuit structure to determine if a fault exists in the integrated circuit structure using a probe tool, forming an electrical connection between the integrated circuit structure and the substrate using a laser tool, and determining a location of the fault in the integrated circuit structure using a scanning electron microscope.